|
Tác giả CN
| Kumar, Shobha |
|
Nhan đề
| Formal Probabilistic Timing Verification in RTL / Jayanand Asok Kumar and Shobha Vasudevan |
|
Mô tả vật lý
| From p.138-160 |
|
Tác giả(bs) CN
| Vasudevan, Shobha |
|
Nguồn trích
| Computer-Aided Design of Integrated Circuits and Systems-
Số: 5
Tập: 32
Năm: 2013 |
|
|
000
| 00000nab#a2200000ui#4500 |
|---|
| 001 | 101504 |
|---|
| 002 | 21 |
|---|
| 004 | 2305F718-3156-40B4-AE76-94C51C80485E |
|---|
| 005 | 201901100839 |
|---|
| 008 | 081223s vm| vie |
|---|
| 009 | 1 0 |
|---|
| 039 | |y20190110083944|zngavt |
|---|
| 100 | |aKumar, Shobha |
|---|
| 245 | |aFormal Probabilistic Timing Verification in RTL / |cJayanand Asok Kumar and Shobha Vasudevan |
|---|
| 300 | |aFrom p.138-160 |
|---|
| 700 | |aVasudevan, Shobha |
|---|
| 773 | |tComputer-Aided Design of Integrated Circuits and Systems|d2013|v32|i5 |
|---|
| 890 | |c1 |
|---|
|
|
Không tìm thấy biểu ghi nào