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Computer-Aided Design of Integrated Circuits and Systems, Tập 33, Số 4, 2014
Mục lục:
DòngNội dung
1Guest Editorial Special Section on Contemporary and Emerging Issues in Physical Design
2Characterizing VeSFET-Based ICs with CMOS-Oriented EDA Infrastructure / Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly
3Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment / Yu-Guang Chen and others
4On the Deployment of On-Chip Noise Sensors / Tao Wang and others
5Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem / Logan Rakai and others
6Effective Method for Simultaneous Gate Sizing and Vth Assignment Using Lagrangian Relaxation / Guilherme Flach and others
7PushPull: Short-Path Padding for Timing Error Resilient Circuits / Yu-Ming Yang, Iris Hui-Ru Jiang, Sung-Ting Ho
8Mixed-Crossing-Avoided Escape Routing of Mixed-Pattern Signals on Staggered-Pin-Array PCBs / Kan Wang and others
9Reachability-Based Robustness Verification and Optimization of SRAM Dynamic Stability Under Process Variations / Yang Song, Hao Yu, Sai Manoj Pudukotai DinakarRao
10Accelerated Performance Evaluation of Fixed-Point Systems With Un-Smooth Operations / Karthick Nagaraj Parashar, Daniel Menard, Olivier Sentieys
11Optimizing the Antenna Area and Separators in Layer Assignment of Multilayer Global Routing / Wen-Hao Liu and Yih-Lang Li
12Error Detection and Recovery for ECC: A New Approach Against Side-Channel Attacks / Kun Ma and Kaijie Wu
13Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States / Irith Pomeranz
14Latency Analysis for Sequential Circuits / Alexander Finder, André Sülflow, Görschwin Fey