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Computer-Aided Design of Integrated Circuits and Systems, Tập 33, Số 3, 2014
Mục lục:
DòngNội dung
1Migration-Aware Loop Retiming for STT-RAM-Based Hybrid Cache in Embedded Systems / Keni Qiu and others
2Error Model Guided Joint Performance and Endurance Optimization for Flash Memory / Liang Shi and others
3Fast Online Synthesis of Digital Microfluidic Biochips / Daniel T. Grissom and Philip Brisk,
4TPaR: Place and Route Tools for the Dynamic Reconfiguration of the FPGA’s Interconnect Network / Elias Vansteenkiste and others
5Importance Boundary Sampling for SRAM Yield Analysis with Multiple Failure Regions / Jian Yao, Zuochang Ye, Yan Wang
6A Novel Layout Decomposition Algorithm for Triple Patterning Lithography / Shao-Yun Fang, Yao-Wen Chang, Wei-Yu Chen
7A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing / Jordi Cortadella, Sergio Gomez, Francesc Moll
8A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems / Deokjin Joo,Taewhan Kim, Senior Member
9Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip / Mahdi Nikdast and others
10Pre-Silicon Bug Forecast / Qi Guo and others
11Retiming for Delay Recovery After DfT Insertion on Interdie Paths in 3-D ICs / Brandon Noia and Krishnendu Chakrabarty
12Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs / Li-Ren Huang and others